Synopsys Unleashes Ethernet On Steroids With 1.6T Blueprint To Turbocharge AI Training

Semiconductor design outfit Synopsys is targeting datacenter customers with a 1.6 terabit (1.6T) Ethernet blueprint intended to enable chips for demanding AI networking applications.

The California-based company, best known as a provider of electronic design automation (EDA) tools, claims its latest work is the first complete 1.6T Ethernet IP solution for chip designers to build products with an eye on the burgeoning bandwidth demands of AI processing.

Although the IEEE is not expected to finalize the latest iteration of the 1.6 Tb Ethernet standard until 2026, Synopsys says its design provides chipmakers with the IP they need today to create the fast networking silicon. A baseline set of features is expected to be completed this year via the 802.3dj task force.

Synopsys has based its design on the latter, supporting 4 x 400G, 2 x 800G, and 1.6T Ethernet rates with 112 Gbps and 224 Gbps SerDes. As well as 1.6T media access control (MAC) and physical coding sublayer (PCS) components, the solution has 224G Ethernet PHY and verification IP.

With the current craze for AI driven by the latest generational models, data networks in the cloud datacenters where these are most commonly hosted have felt the strain from the massive volumes of data required for training them.

This calls for significantly faster Ethernet speeds in order to keep pace with the ever-increasing data demands, according to Synopsys senior VP of IP marketing and strategy John Koeter.

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"Our complete IP solution for 1.6T Ethernet, pre-verified subsystems... allow designers to confidently integrate the necessary functionality into their SoCs with less risk," he claimed.

The move has been welcomed by industry consortium the Ethernet Alliance.

"With growing demands from large language modeling, HPC simulation, and AI training in hyperscale datacenters, network boundaries are crossing over the terabits per second threshold," chairman Peter Jones, also a Distinguished Engineer at Cisco, said in a statement.

"The availability of development tools capable of meeting these needs is critical to the success of next-generation Ethernet standards addressing this market."

Synopsys said that its 1.6T Ethernet MAC and PCS components cut the required silicon area by 50 percent while reducing latency by 40 percent via a patented Reed-Solomon Forward Error Correction architecture.

All the components of the 1.6T Ethernet blueprint are available now, and it has already been adopted by multiple customers, Synopsys claimed.

The design has been validated with multiple hardware platforms, PHYs, and Ethernet verification suites across a broad range of production processes and foundries, the company said. ®