Rambus Offers Chip Designers A Drop-in PCIe 6.0 Subsystem

While PCIe 5.0 continues to gain traction, Rambus has made available a PCIe 6.0 Interface Subsystem for incorporation in third-party hardware. It comprises PHY and controller blocks, with the PHY also supporting the latest CXL 3.0 specifications.

The PCIe 6.0 specifications were released by the PCI-SIG consortium early this year, but it typically takes 12-18 months following this for products to come to market, meaning that the first devices are likely to ship sometime in 2023.

Rambus is targeting SoC designers with the PCIe 6.0 Interface Subsystem, which the company claimed is optimized for latency, power and area, and supports the full feature set of PCIe 6.0.

These features include double the bandwidth over PCIe 5.0, with a 64GT/s raw data rate per lane and the use of PAM4 signal encoding. It is expected to show the most benefit in demanding data-intensive applications such as high performance computing (HPC) and AI/ML by enabling higher bandwidth for hardware such as GPUs and NVMe SSDs.

• AMD's Ryzen V3000 goes head to head with Intel's embedded chips on power, oomph
• Intel details 12th Gen Core SoCs optimized for edge applications
• AMD refreshes desktop CPUs with 5nm Ryzen 7000s that can reach 5.7GHz with 16 cores
• Intel aims Flex datacenter GPUs at video, game streaming

"The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of datacenter architectures requiring ever higher levels of performance," said Scott Houghton, Rambus general manager for Interface IP.

Within the subsystem itself, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the data they carry, Rambus said. Meanwhile, the PHY, or physical layer, has full support for CXL 3.0 to enable chip-level solutions for cache-coherent memory sharing, expansion and pooling.

CXL, or Compute Express Link, builds on the PCIe standard but adds multi-tiered switching and switch-based fabrics, along with improved memory sharing and pooling capabilities. Combined, these three key features enable new use models and increased flexibility in datacenter architectures, Rambus said.

For engineers, the number of signal integrity and power integrity issues quickly becomes a headache as data rates rise, and so designing for 64 GT/s operation can be extremely difficult. Rambus claims that it has done all the hard work with its Interface Subsystem, offering chip designers an easy to integrate solution that provides both PCIe 6.0 and CXL 3.0 compatibility. ®