MIPS Discloses First RISC-V Chips Coming In Q4 2022

MIPS is back, but this time the company is bringing processors to market based on the RISC-V open instruction set architecture, rather than the MIPS architecture the chip designer is synonymous with.

The current incarnation* of MIPS proclaimed its entry to the RISC-V market with a preview of the first products in its new eVocore processor line, which initially comprises two multiprocessor IP cores, the eVocore P8700 and I8500.

MIPS said that the new processors are designed for high-performance, real-time compute applications such as networking, datacenter, and the automotive industry.

To deliver on this goal, the eVocore IP cores was developed around scalability. MIPS said it aims to allow customers to specify custom chip configurations that combine coherent clusters of the multi-threaded, multi-core CPUs to match their power and performance requirements.

Custom configurations might also extend to other types of CPU core, with MIPS stating that it has designed the new cores to support heterogeneous combinations of eVocore processors and other accelerators. A Coherence Manager is part of the design, and this maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices.

The RISC-V architecture also provides for customization in the form of user defined instructions (UDIs), and MIPS said this would be useful in many high-end applications, while also keeping full compatibility with standard RISC-V development tools and software libraries.

MIPS is keeping some details close to its chest at the moment, but the eVocore P8700 is branded as the "superscalar performance" design, while the eVocore I8500 carries the tagline of "best-in-class performance efficiency."

To deliver on its superscalar performance, MIPS says the eVocore P8700 features a deep instruction pipeline with multi-issue out-of-order execution with multi-threading, and can scale up to 64 clusters with 512 cores and 1,024 threads.

The company claims this core design offers single-threaded performance greater than anything currently available in other RISC-V CPU IP offerings, but has not backed this up with any data.

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Meanwhile, the eVocore I8500 features in-order execution and emphasizes power efficiency for use in system-on-chip (SoC) applications. MIPS said that each I8500 core combines multi-threading and an efficient triple-issue pipeline to deliver "outstanding" computational throughput.

The eVocore P8700 is set to be available from Q4 2022, but no date was specified by MIPS for the eVocore I8500.

MIPS CEO Desi Banatao said his company is targeting the high-performance segment of the processor market with its switch to the RISC-V architecture.

"By leveraging our differentiation in real-time features, hardware virtualization, functional safety and security technologies, we can offer compelling products for automotive, edge compute, networking and switching, and large-scale computing systems," Banatao added.

The move adds to the growing momentum behind RISC-V, with India announcing plans recently to become a major player in the RISC-V chip market, while Intel in February joined RISC-V International, the governing body that oversees development of the architecture, as a premier member. ®

Bootnote

*The original MIPS was founded in 1984 to develop and manufacture RISC processors based on its MIPS architecture. The firm was acquired by SGI in 1992, before being spun out again in 1998 as a chip design outfit.

In 2013 the company was purchased by Imagination Technologies, but sold to a venture capital firm in 2017, before being purchased soon after by Wave Computing in 2018. Wave Computing then filed for bankruptcy in 2020, before renaming itself MIPS. Got that?