Micron Samples First DRAM Built Using 1-beta Process Node

Micron is shipping samples of memory chips fabricated with its 1β (1-beta) production node, claiming it delivers better performance, bit density, and power efficiency, while remaining coy about the exact dimensions involved.

The memory chipmaker said its 1β DRAM technology node achieved "mass production readiness" in September, and it has since dispatched LPDDR5X samples to its smartphone manufacturer and chipset customers for products expected to come to market in 2023.

In the future, Micron will expand the memory products manufactured on this node, from LPDDR to DDR5 to HBM and graphics memory. The 1β products will be manufactured initially at Micron's fabrication plant in Hiroshima, Japan.

The first LPDDR5X products boast a 16Gb per die capacity and a data rate of 8.5Gbps, and are claimed to deliver a 15 percent power efficiency improvement and upwards of a 35 percent bit density improvement when compared with products manufactured with the previous 1α (1-alpha) process node technology.

According to Micron's vice president of DRAM process integration, Thy Tran, this was achieved through the use of cutting-edge pattern multiplication techniques, new processes, new materials, and more advanced equipment to shrink down the memory cell array.

"We can aggressively scale both the memory cell in terms of size, but also the rest of the circuitry in the die to save space and deliver the smallest die possible for a given density while optimizing for power and performance improvements," said Tran.

Beyond mobile, 1β will enable low-power, high-performance DRAM for a wide range of applications from mobile phones to intelligent vehicles and datacenters, Micron claimed.

But when asked to explain what 1α and 1β mean in terms of actual sizes and scaling, Micron declined to be drawn, with Tran responding: "I can definitely say that this is more aggressive than the 1α shrink, and I'll leave it at that."

• Hot DRAM, Micron promises $100b for 'largest chip fab in US history'
• Taking CHIPS Act cash? You're banned from planting advanced fabs on Chinese soil
• PC shipments fall at fastest rate ever as businesses slam wallets shut
• The great semiconductor drought may be about to break

“It's not always about the exact dimensions and size of either the memory cell or the die, and in the end it's about delivering higher density at a competitive cost point, and meeting the performance and power efficiency that the customer needs,” she added.

Micron did reveal that the 1β production node does not use extreme ultraviolet (EUV) lithography, as had been expected by some in the industry, but this is likely to happen with the following 1γ (1-gamma) node technology.

"Our strategy is to deploy [EUV] at the right time. We can foresee that our 1γ node will intersect EUV, but we continue to evaluate in terms of performance and cost points, but that is definitely on the map," Tran said.

The question of node size is a vexed one as far as DRAM goes, as explained by The Register's sister site Blocks & Files. This is because DRAM relies on charge stored on capacitors to represent individual bits, and shrinking those capacitors below a certain size means that they cease to function as required.

For this reason, DRAM components have been stuck at process nodes of 10nm or above for several years, and shrinking much further will likely require a breakthrough in new materials.

Earlier this month, Micron unveiled plans for a $100 billion memory chip fabrication plant in New York State, the building of which will take at least 20 years.

For the near term, however, Micron is cutting investment in additional production capacity, in line with many other memory chipmakers, as the economic outlook worsens. It said it will cut capex for next year by more than 30 percent to about $8 billion. ®