AMD Says Transistor Tech Will Keep Moores Law Alive For 6 To 8 Years

Chipmaker AMD has hinted that new transistor technology will keep Moore's Law alive for the next six to eight years, but as one might guess, it will cost more.

Meanwhile, the company still plans to market new chips based on its Zen 4 architecture next year, including Bergamo, which is intended to compete against Arm-based chips for cloud-native computing.

In an interview with Wells Fargo analyst Aaron Rakers at the financial outfit's TMT Summit, AMD CTO Mark Papermaster talked about future directions and the company's near-term roadmap.

Rakers asked about the Zen family and its chiplet-based architecture versus the monolithic architecture seen with Intel's CPUs, and whether this would continue to serve AMD for the next four to five years, or whether another novel approach might be needed.

"Innovation always finds its way around barriers," Papermaster said. "I can see exciting new transistor technology for the next – as far as you can really plot these things out – about six to eight years, and it's very, very clear to me the advances that we're going to make to keep improving the transistor technology, but they're more expensive," he said.

In the past, chipmakers like AMD and Intel could double the transistor density every 18 to 24 months and stay within the same cost envelope, but that is not the case anymore, Papermaster claimed.

"So, we're going to have innovations in transistor technology. We're going to have more density. We're going to have lower power, but it's going to cost more. So how you put solutions together has to change," he said.

Partly, this has already been addressed with AMD's Infinity architecture, according to Papermaster, which enabled the modular approach of the chiplet architecture that sees a chip built from multiple dies, possibly manufactured using different process nodes, linked together using a standardized interconnect.

"Chiplets is really a way to just rethink about how the semiconductor industry is going forward," he said.

This "will keep innovation going and we'll keep, I'll say, a Moore's Law equivalent, meaning that you continue to really double that capability every 18 to 24 months, [this] is the innovation around how the solution is put together," he added.

What this means is that the future will be heterogeneous, according to Papermaster, although we have already gone down this route at a system level if you look at the way CPUs and GPUs are paired together to accelerate certain workloads.

"So you're going to have to use accelerators, GPU acceleration, specialized functions, adaptive compute like we acquired with Xilinx, which closed in February this year, he said.

"Those elements are going to have to come together, and you're going to see tremendous innovation in how those come together and it really will keep us on pace, and we actually have to, because you can just look at the demands of computing, they haven't slowed down one iota. In fact, they're escalating rapidly with AI becoming more and more prevalent," Papermaster explained.

Meanwhile, hyperscale cloud customers are increasingly asking for platforms optimized for key workloads, especially around performance and power efficiency, and this has been shaping AMD's development, according to Papermaster.

Talking about the newly launched fourth-generation Epyc "Genoa" processor, he claimed it gives a total cost of ownership advantage for customers, and delivers it in a timely way.

"What Genoa does is leverages the fact that we took the CPU complex and moved it from 7nm to 5nm. Remember what I said earlier, new transistors are still giving you more density and more performance per watt. So we combine 5nm on the CPU with our design techniques, and we improved 48 percent on the compute efficiency," Papermaster said.

"So it's a huge generational gain on performance per watt. And that's how we're able to go from 64 cores in a single socket to 96 cores in a single socket."

But the company is also trying to offer more choices for hyperscale customers.

"Our stack has incredible coverage from top to bottom now, with the kind of granularity that our customers need to really cover hyperscale through enterprise, and we are adding in first half of this year, what we call Bergamo, which will be with our Zen 4c," he said.

Bergamo is still Zen 4, it runs a code just like Genoa, but it's half the size, Papermaster added, which will compete head-to-head with Graviton and Arm-based solutions where maximum frequency is not required.

"Say you're running workloads like Java workloads, or throughput workloads that don't have to run peak frequency, but you need a lot of cores. So we're adding that in first half of 2023. And then later in 2023, we're adding the Siena, which is a variant targeted to telecom space. So we're really, really excited about our TAM growth in server," he said.

Siena, which was disclosed at AMD's Financial Analyst Day event in June, is apparently designed for intelligent edge and telecommunications applications, and so will potentially compete against Intel's Xeon D family, which have built-in networking and quality of service (QoS) functions.

Papermaster also mentioned Genoa-X, which is a version of the fourth-generation Epyc processors but with upwards of 1GB of L3 cache stacked directly on top of the CPU die to boost high-performance workloads like EDA (electronic design automation) or database processing. This chip is also expected in 2023.

In response to a question about AMD's acquisition of FPGA specialist Xilinx and networking vendor Pensando, Papermaster said "I don't think people quite realize how important those acquisitions were in terms of rounding out the AMD portfolio."

With Xilinx, it is "adaptive compute", he claimed, explaining that it wasn't just about FPGAs, but the ability for Xilinx to combine an FPGA with Arm processor cores or even implement Arm cores using an FPGA.

"And with Pensando, we have a programmable SmartNIC that's absolutely a leadership play. It's being adopted in hyperscale, and it has 144 P4 engines," Papermaster said. P4 is a programming language for controlling packet forwarding planes in networking devices, and likely to play a part in micro services in the datacenter, he added.

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Finally, Papermaster hinted that AMD has not completely given up on an Arm-based server processor.

"As some may recall, we had our road map when you go back eight, nine years ago, with both Arm and x86, and we defeatured the Arm in our CPU road map because the ecosystem still had too far to go," he said.

"We could have made that. We had a design approach that was going to make the custom Arm design for AMD equally performant to the x86, but the ecosystem wasn't there. So we kept our focus on x86, and we said, let's watch the space in Arm," he added, noting that "Arm is now developing more of a robust ecosystem."

Papermaster said AMD's current strategy is to "keep our x86 performance going as such that it's a leadership capability" but added that "if someone has reasons that they want Arm, we have our custom group, and we're happy to work with them to implement in our base solution. We're not not married to an ISA." ®