Proposed RISC-V Vector Instructions Crank Up Computing Power On Small Devices

RISC-V looks set to be extended to bring more computing power to applications on smaller devices.

The Zve collection of software instructions, right now under public review, provide vector math processing for embedded devices and microcontrollers.

RISC-V is an open-source, royalty-free instruction set architecture for CPU cores: RISC-V International sets the spec, and semiconductor designers are free to implement it as they see fit in their processors and system-on-chips.

The ISA is structured as a set of extensions, and CPU designers can pick and choose which extensions they wish to implement to suit the software their components will likely run. If you want to make a core capable of natively booting a usable Linux system, for instance, you'll want to implement at least the base set of integer instructions plus the atomic operations and multiplication and division sets, and a few others for good measure.

The Zve extensions provide 32-bit and 64-bit integer, fixed-point, single-precision, and double-precision floating-point vector operations suitable for modest CPU cores. There is, separately, a full-blown vector math extension that was frozen for public review last month. Zve is a more modest spin of that so that it can be implemented in smaller cores.

"Applications such as AI, vision processing, security and voice will all benefit from the Zve extensions," said Ted Speers, technical fellow at Microchip Technology, which makes chips with RISC-V-compatible cores.

Zve extensions address a bigger demand for faster computing on the network edge where data from sensors, especially in IoT and automotive applications, needs to be processed with low latency and low power, Speers said.

Vector instructions are widely used to handle demanding applications in areas that include graphics and high-performance computing.

"Their purpose is to bring the power of RISC-V vector extensions to small devices by only supporting a subset of the vector extensions," Speers said.

The Zve extensions will lead to new types of chips tailored to meet the stringent cost and power demands and increasing performance, Speers said, adding that it will drive "a new ecosystem of tools and libraries because one RISC-V vector architecture can be applied to all domains – both high-end and low-end."

• First RISC-V computer chip lands at the European Processor Initiative
• New release of SweRVolf RISC-V SoC project aims for lower barrier to entry
• China to push RISC-V to global prominence – but maybe into a corner, too, says analyst
• Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors

The Zve extensions are currently in public review, which ends on November 4.

RISC-V's modular approach helps engineers cut down the size, complexity, and cost of their CPU cores.

"You would pick a fixed function where you know the workload before building the hardware. That's how companies and partners build RISC-V," said James Prior, senior director of product marketing and communications at SiFive, which produces RISC-V chips for customers.

The Zve extensions could be used for applications like audio, voice or image processing, similar to those handled by digital signal processors in smartphones, Prior said. For example, Zve extensions could be used to make a chip for smart speakers. Suffice to say, rival architectures, such as Arm, also offer vector instructions for large and small CPU cores.

SiFive already offers products that support the aforementioned larger RVV vector extension.

In an online SiFive design tool, customers can tailor a RISC-V CPU core to their needs, and request the corresponding RTL data to evaluate it in an FPGA. It's possible SiFive could provide Zve extensions from this tool for a custom embedded workhorse; Prior couldn't comment if or when SiFive would offer that option to customers.

The Zve approach is more elegant and efficient than full-bore SIMD (single instructions multiple data), which you might see in x86 processors to crank up performance, Prior said. He likened the RISC-V approach to vector operations to Cray supercomputers in the 1970s, an argument we've heard before.

The RISC-V effort to create vectorized compilers and libraries for high-end devices can be also applied to Zve, which makes it easy to write software for a full range of compute performance needs, Microchip's Speers said.

Speers said Microchip has not disclosed plans for use of the Zve extensions in its products. ®